#include "config.h"

// CONFIG1H
#pragma config FOSC      = HS2      // Oscillator (HS oscillator (High power))
#pragma config FCMEN     = OFF      // Fail-Safe Clock Monitor (Disabled)
#pragma config IESO      = OFF      // Internal External Oscillator Switch Over Mode (Disabled)
#if __PLL_ENABLED
#pragma config PLLCFG    = ON       // PLL x4 Enable bit (Enabled)
#else
#pragma config PLLCFG    = OFF      // PLL x4 Enable bit (Disabled)
#endif

// CONFIG1L
#pragma config RETEN     = OFF      // VREG Sleep Enable bit (Ultra low-power regulator is Disabled (Controlled by REGSLP bit))
#pragma config INTOSCSEL = LOW      // LF-INTOSC Low-power Enable bit (LF-INTOSC in Low-power mode during Sleep)
#pragma config SOSCSEL   = DIG      // SOSC Power Selection and mode Configuration bits (Digital (SCLKI) mode)
#pragma config XINST     = OFF      // Extended Instruction Set (Disabled)

// CONFIG2L
#pragma config PWRTEN    = OFF      // Power Up Timer (Disabled)
#pragma config BOREN     = SBORDIS  // Brown Out Detect (Enabled in hardware, SBOREN disabled)
#pragma config BORV      = 3        // Brown-out Reset Voltage bits (1.8V)
#pragma config BORPWR    = ZPBORMV  // BORMV Power level (ZPBORMV instead of BORMV is selected)

// CONFIG2H
#pragma config WDTEN     = OFF      // Watchdog Timer (WDT disabled in hardware; SWDTEN bit disabled)
#pragma config WDTPS     = 1048576  // Watchdog Postscaler (1:1048576)

// CONFIG3H
#pragma config CANMX     = PORTC    // ECAN Mux bit (ECAN TX and RX pins are located on RC6 and RC7, respectively)
#pragma config MSSPMSK   = MSK7     // MSSP address masking (7 Bit address masking mode)
#pragma config MCLRE     = ON       // Master Clear Enable (MCLR Disabled, RG5 Enabled)

// CONFIG4L
#pragma config STVREN    = ON       // Stack Overflow Reset (Enabled)
#pragma config BBSIZ     = BB1K     // Boot Block Size (1K word Boot Block size)

// CONFIG5L
#pragma config CP0       = OFF      // Code Protect 00800-01FFF (Disabled)
#pragma config CP1       = OFF      // Code Protect 02000-03FFF (Disabled)
#pragma config CP2       = OFF      // Code Protect 04000-05FFF (Disabled)
#pragma config CP3       = OFF      // Code Protect 06000-07FFF (Disabled)

// CONFIG5H
#pragma config CPB       = OFF      // Code Protect Boot (Disabled)
#pragma config CPD       = OFF      // Data EE Read Protect (Disabled)

// CONFIG6L
#pragma config WRT0      = OFF      // Table Write Protect 00800-01FFF (Disabled)
#pragma config WRT1      = OFF      // Table Write Protect 02000-03FFF (Disabled)
#pragma config WRT2      = OFF      // Table Write Protect 04000-05FFF (Disabled)
#pragma config WRT3      = OFF      // Table Write Protect 06000-07FFF (Disabled)

// CONFIG6H
#pragma config WRTC      = OFF      // Config. Write Protect (Disabled)
#pragma config WRTB      = OFF      // Table Write Protect Boot (Disabled)
#pragma config WRTD      = OFF      // Data EE Write Protect (Disabled)

// CONFIG7L
#pragma config EBTR0     = OFF      // Table Read Protect 00800-01FFF (Disabled)
#pragma config EBTR1     = OFF      // Table Read Protect 02000-03FFF (Disabled)
#pragma config EBTR2     = OFF      // Table Read Protect 04000-05FFF (Disabled)
#pragma config EBTR3     = OFF      // Table Read Protect 06000-07FFF (Disabled)

// CONFIG7H
#pragma config EBTRB     = OFF      // Table Read Protect Boot (Disabled)
